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銆�銆�Altera adds hard floating point to FPGAs

銆�銆�Altera is shipping Arria 10 FPGAs withhardened floating-point DSP blocks, but customers will have to wait for designflows.

銆�銆�The DSP block, which is IEEE 754-compliant,will also be in Stratix 10 FPGAs.

銆�銆�Up to 1.5 Tflop is claimed in Arria and 10Tflop in Stratix.

銆�銆�“Designers are able to choose either fixed or floating-point modesand the floating point blocks are backwards compatible with existing designs,”said Altera. “The inclusion enable customers to use FPGAs to address problemsin big data analytics, seismic modeling for oil and gas industries andfinancial simulations.”

銆�銆�Floating-point design flows, includingdemonstrations and benchmarks, for the floating-point blocks will be availablein the second half of this year.

銆�銆�“Customers can start designing today with Arria 10 FPGAs using softimplementations of floating point and then seamlessly migrate to hardenedfloating point implementation when the design flows are available.”

銆�銆�The firm’s DSP Builder Advanced Blocksetwill offer a model-based design flow allowing designers to go from systemdefinition and simulation to system implementation using MathWorks Simulink.

銆�銆�20nm Arria 10 can also include a dual-corehard ARM Cortex-A9, serial transceivers up to 28.3Gbit/s, backplane support upto 17.4Gbit/s, and support for DDR4 at 2.666Gbit/s.